An integrated circuit may be subjected to an Electrostatic Discharge (ESD) event both in the manufacturing process and in the ultimate system application. The energy associated with this transient discharge can easily damage the fragile devices present in a modern integrated circuit (IC). External pins or pads form the connection points for the integrated circuit to the outside world and therefore serve as pathways for ESD events. An ESD event applied to a pad may couple a voltage exceeding a thousand volts to circuitry connected to the pad. Devices and circuits connected to Input/Output (I/O) pads, including the output pull-down and pull-up buffers, tend to be particularly susceptible to ESD damage. Modern integrated circuits typically require additional ESD circuitry in order to harmlessly shunt ESD currents around the fragile buffers.
FIG. 1 illustrates a simple Input/Output (I/O) circuit 100. The I/O pad 108 is connected between a positive power supply rail (VDD) 104 and a negative power supply rail (VSS) 106. An N-channel MOSFET (NMOSFET) Transistor 114 is connected between the I/O pad 108 and the VSS power supply rail 106. A P-channel MOSFET (PMOSFET) 118 is connected between the I/O pad 108 and the VDD power supply rail 104. NMOSFET 114 serves as the output pull-down buffer while PMOSFET 118 serves as the output pull-up buffer. The gates of NMOSFET 114 and PMOSFET 118 are each connected to output predriver circuitry (not shown).
FIG. 1 also illustrates a prior art ESD protection network consisting of ESD diodes 110 and 112 and an active MOSFET rail clamp circuit 116. Diodes 110 and 112 are used to shunt ESD current between the I/O pad 108 and the VDD and VSS power rails. The active MOSFET rail clamp 116 is comprised of an ESD detector circuit 102 and a shunting device 103 connected between the VDD rail 104 and the VSS rail 106. The rail clamp circuit 116 is used to shunt ESD current between the power supply rails 104 and 106 and thereby protect sensitive internal elements in the IC from damage. The shunting device 103 is typically a large NMOSFET. An example of such a rail clamp circuit is illustrated in FIG. 3 of U.S. Pat. No. 5,946,177 issued to Miller et al. on Aug. 31, 1999, which is incorporated by reference herein. The rail clamp circuit in the Miller et al. patent includes a shunting device and an ESD detector circuit. The ESD detector circuit senses an ESD event and activates the shunting device into a low resistance conductive state in response to the ESD event.
Integrated circuits are often most susceptible to damage during positive ESD events coupled onto an I/O pad referenced to grounded VSS. The primary intended ESD dissipation path for this event in I/O circuit 100 is as follows. The I/O pad 108 voltage rises rapidly as the positive ESD event is applied. Diode 110 forward biases, allowing the VDD rail voltage to increase as well. The ESD detector circuit 102 in rail clamp 116 senses the ESD event, and turns on shunting device 103, allowing the transient ESD current to flow harmlessly between VDD and VSS. During this ESD event, the I/O pad voltage rises to a peak level set by the sum of the voltage drops as the peak current of the applied ESD event flows through the intended dissipation path.
It is important to note that the NMOSFET buffer 114 provides an alternate dissipation path for the ESD event described above, and for this reason, is often the most fragile device in the I/O circuit. During the ESD event, the NMOSFET 114 may conduct as a lateral parasitic NPN bipolar transistor 120, with the NMOSFET drain diffusion, source diffusion, and local P-type substrate region forming the lateral bipolar collector, emitter, and base regions, respectively. While the parasitic NPN transistor 120 is shown as device separate from NMOSFET 114 in FIG. 1, it should be understood that these are formed from a single device with two modes of electrical operation. FIG. 2 shows a typical Current-Voltage (IV) curve for a NMOSFET output buffer transistor. The gate terminal is assumed grounded during the measurements. As the drain (I/O pad) voltage for the NMOSFET rises due to an applied ESD event, the device initially conducts via avalanche generation at the drain to substrate diode junction. The avalanche region 202 is shown in FIG. 2. Avalanche generated holes drift in the P-substrate region through local spreading resistance 115 (FIG. 1) to the VSS rail, elevating the local substrate potential. Eventually, at a threshold known as first breakdown (V.sub.T1, I.sub.T1), the NPN base-emitter junction diode will forward bias, signaling the turn-on of the lateral parasitic bipolar transistor. The device will then exhibit a sudden negative resistance transition and enter the parasitic lateral bipolar region of operation 204. The parasitic bipolar transistor may be capable of conducting significant ESD current in this bipolar region before failure. However, if the drain voltage rises above a second current-voltage threshold, defined as V.sub.T2 -I.sub.T2, the device will suffer permanent thermal damage.
In summary, the ESD protection network in FIG. 1 utilizes a series combination of diode 110 and rail clamp 116 to provide the primary ESD dissipation path for positive I/O events with respect to grounded VSS. The lateral NPN transistor 120 parasitic to the pull-down buffer NMOSFET 114 provides a parallel but potentially fragile alternate conduction path. This fragile device will fail if the I/O pad voltage exceeds V.sub.T2, the ESD failure voltage for the parasitic lateral NPN. This failure voltage defines the margin of operation for the primary ESD dissipation path. Therefore, diode 110, rail clamp 116, and their interconnections must be designed to dissipate the required ESD current (typically amperes) while holding the I/O pad voltage to below V.sub.T2 for the pull-down buffer (typically 6-10V). This requirement is becoming increasingly difficult to meet. As integrated circuit technologies have scaled, the lateral NPN second breakdown voltage and current threshold (V.sub.T2, I.sub.T2) have reduced dramatically, often to the point where the intended ESD protection path can no longer provide adequate ESD protection. Therefore, a limitation with the conventional protection circuit 100 is poor ESD resistance due to the increasing ESD susceptibility of the NMOSFET pull-down buffer 114.
FIG. 3 illustrates a second type of I/O circuit 300 which is designed to tolerate input voltages in excess of the maximum specified power supply voltage for the MOSFETs which form the integrated circuit. For example, in certain applications, the IC may operate with a maximum internal power supply voltage (VDD) of 3.3V but must tolerate up to 5.5V at the I/O pads. In this mixed voltage I/O, both the pull-up and pull-down buffers must be modified as compared to the I/O described in FIG. 1. The pull-down buffer is formed by two NMOSFETs placed in a series or cascoded configuration. A first NMOSFET 313 and a second NMOSFET 314 are connected in series between the I/O pad 308 and the VSS power supply rail 306. The gate of NMOSFET 313 is connected to the positive power supply rail VDD 304. The gate of NMOSFET 314 is connected to output predriver circuitry (not shown). The cascoded NMOSFETs provide a convenient means of stepping a higher than VDD input voltage across two gate oxides. For example, with 5.5V at the I/O pad, and 3.3V at the gate of NMOSFET 313, no voltage in excess of the 3.3V allowable maximum is seen across the gate oxide of either NMOSFET 313 or NMOSFET 314.
The PMOSFET pull-up buffer in FIG. 3 is also modified as compared to the buffer in FIG. 1. The modifications are required in order to eliminate forward bias conduction in the parasitic P+ drain diffusion to NWELL diode in the event the I/O pad voltage is elevated above VDD. PMOSFET 318 is placed in an NWELL control by tracking well circuit 319. The tracking well circuit holds the NWELL of PMOSFET 318 at VDD potential whenever the I/O pad voltage is less than or equal to VDD. In the event the I/O pad rises above VDD, the tracking well circuit 319 ensures that the PMOSFET NWELL voltage tracks the I/O pad voltage. This prevents unwanted I/O pad to VDD conduction through the parasitic diode.
FIG. 3 also illustrates a prior art ESD protection network for this mixed voltage I/O consisting of diode 312, diode string 310, and active MOSFET rail clamp circuit 316. Diode string 310 is implemented to ensure no forward bias conduction from the I/O pad to VDD under the specified VDD level and the maximum tolerable I/O pad voltage. As described above, integrated circuits are often most susceptible to damage during positive ESD events coupled onto the I/O pad referenced to grounded VSS. The intended ESD dissipation path for this event in protection circuit 300 is as follows. The I/O pad 308 voltage rises rapidly as the ESD event is applied. Diode string 310 forward biases as the I/O pad voltage rises above the string stand-off voltage. The ESD detector circuit 302 in rail clamp 316 senses the ESD event, and enables shunting device 303, allowing the transient ESD current to flow between VDD and VSS. During this ESD event, the I/O pad voltage rises to a peak level set by the peak current of the applied ESD event, the stand-off voltage of the diode string, and the net resistance of the intended dissipation path.
As in the case of a single NMOSFET pull-down buffer (FIG. 1), the cascoded NMOSFET buffer (FIG. 3) can turn on and conduct as a lateral parasitic bipolar transistor during a positive ESD event between the I/O pad and VSS. This provides a potentially fragile alternate ESD conduction path in parallel with the intended primary conduction path. As shown in FIG. 3, a lateral parasitic bipolar transistor 320 is formed from components of both NMOSFETs 313 and 314. The lateral NPN collector, emitter, and base are formed from the drain of NMOSFET 313 (tied to the I/O pad), the source of NMOSFET 314 (tied to VSS), and the local P-substrate region, respectively. It is known that the lateral NPN formed from cascoded pull-down buffers typically exhibit a higher bipolar turn-on voltage (V.sub.T1) than the single NMOSFET buffer configuration. (See, S. Voldman, J. Never, S. Holmes, and J. Akkisson, "Linewidth Control Effects on MOSFET ESD Robustness," the 1996 EOS/ESD Symposium Proceedings, p. 101; and W. Anderson and D. Krakauer, "ESD Protection for Mixed-Voltage I/O Using NMOS Transistors Stacked in a Cascode Configuration," the 1998 EOS/ESD Symposium Proceedings, p. 54.) This is demonstrated in FIG. 4 which compares the bipolar turn-on IV characteristics of example single (Curve A) and cascoded (Curve B) NMOSFET output buffers. The gates of all NMOSFETs are held to VSS during the measurements for Curve A and Curve B. This plot only shows bipolar turn-on characteristics through first breakdown. For clarity, datapoints in the bipolar conduction region are not shown. It can be seen that, in this example data, V.sub.T1 for the single NMOSFET buffer is about 8.0V, while V.sub.T1 for the cascoded NMOSFET buffer is about 11V. This difference in V.sub.T1 is primarily due to the increased emitter to collector spacing in the cascoded NMOSFET configuration as compared to the single NMOSFET configuration. This increased emitter to collector spacing reduces the lateral bipolar gain, and therefore increases the bipolar trigger voltage.
In summary, the ESD protection network in FIG. 3 utilizes a series combination of diode string 310 and rail clamp 316 to provide the primary ESD dissipation path for positive I/O events with respect to grounded VSS. The lateral NPN transistor 320 parasitic to the cascoded pull-down buffer (NMOSFET 313 and NMOSFET 314), provides a parallel but potentially fragile alternate conduction path. This fragile device will fail if the I/O pad voltage exceeds V.sub.T2, the ESD failure voltage for the parasitic lateral NPN 320. As described above, the lateral NPN second breakdown voltage and current threshold (V.sub.T2, I.sub.T2) has reduced dramatically as semiconductor device geometries have scaled, often to the point where the intended ESD protection path can no longer provide adequate ESD protection. Therefore, a limitation with the mixed voltage I/O circuit 300 is poor ESD resistance due to the increasing ESD susceptibility of the cascoded NMOSFET pull-down buffer.
In general, efforts in the industry to maximize the ESD robustness of the pull-down buffer have focused on means to maximize the lateral NPN parasitic bipolar second breakdown failure current (I.sub.T2). This is true for both single and cascoded output buffer configurations. With this approach, the NPN bipolar parasitic to the pull-down output buffer is expected to enter the bipolar conduction region, and dissipate some portion of the total ESD current in parallel with the primary ESD dissipation path. However, the trend of falling I.sub.T2 as process geometries are scaled, may eventually render this approach ineffective.